Manufacturing of an integrated circuit has been largely driven by the need to increase the density of the integrated circuit formed in a semiconductor device. This is typically accomplished by implementing more aggressive design rules to allow larger density of the integrated circuit to be formed. With the significant size shrinkage of the semiconductor devices, the area to form the integrated circuit is dramatically reduced. It results in even more aggressive processes for manufacturing of the integrated circuit to maximize the density of the integrated circuit. Therefore, more interconnect layers of the integrated circuit are needed to be formed to satisfy the miniaturization of manufacturing the integrated circuit.
In fabricating the interconnect layers, which are fabricated during back-end-of-line (BEOL) processes, of the integrated circuit, any defects or particles can render failure of an active device, which is fabricated during front-end-of-line processes (FEOL). Unfortunately, these interconnect defects or particles occurred during the BEOL processes are discovered only after the completeness of costly and time-consuming steps of FEOL processes.
As the density of the integrated circuit increasing and more interconnect layers of the integrated circuit to be formed, the probability of defects or hazardous particles occurred during back-end-of-line processes also increase. Therefore, the yield of manufacturing the integrated circuit in the semiconductor device decreases. Accordingly, improvements in integrated circuits and methods thereof continue to be sought.